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    MonolithIC 3D - Best of West Finalist Suggests Scaling "Up" with 3D

    MonolithIC 3D

    New fabs now cost upwards of $5B. Advancements in lithography and other process steps are so expensive as to demand multi-company collaboration to reduce risk.

    Perhaps the era of scaling down is coming to an end, and perhaps the era of building up is just beginning.

    That’s the premise of MonolithIC 3D, a company with the idea – and the technology – to build vertically. Building up is not new; the industry has been expecting 3D for decades, and is now starting down that path with through-silicon-via (TSV) technology.

    But MonolithIC 3D thinks they have a better approach, and that’s how the company became a finalist for the SEMICON West 2011 “Best of West” Award.

    Company founder Zvi Or-Bach, who previously started Chip Express and eASIC, says that TSV technology is certainly a reasonable approach, but that building layer upon layer of chips would be better. Current silicon processing techniques, with the need for 1000° C temperatures for silicon dioxide growth, preclude creating one “level” of a chip and then building another above it. Since the only other way to build “up” today is TSV, that’s where engineers are working.

    TSV is completely appropriate for finished devices, says Or-Bach, but there may be a better way to accomplish the vertical construction that will lead to high-density transistor stacking.

    MonolithIC 3D’s approach is to start with a conventional wafer with transistors and layers of copper interconnects. Then, a bilayer stack of p- Si and n+ Si on a separate new wafer is constructed using implant and epitaxial processes, and the dopants on the new wafer are activated with normal high-temperature techniques. Next, hydrogen is implanted into the new wafer with p- and n+ Si regions to create the “cut” or “shear” plane. That new wafer is then flipped and oxide-to-oxide bonded atop the first wafer. The stacked wafers are then cleaved at the hydrogen plane, leaving the thin doped layers of mono-crystalline silicon atop the bottom wafer.

    Then “Recessed ChAnnel Transistors (RCATs)” are formed using etch, deposition and other processes typically conducted at <400° C. The gate dielectric and gate electrode are deposited with atomic layer deposition (ALD). Finally, interconnects between the layers (and above the transistors at the second wafer layer) are built.

    According to Or-Bach, this process flow has three unique – and necessary – characteristics: The process steps for transistors that require >400° C, such as implant activation, are done before the wafer-to-wafer layer transfer, ensuring thermal budget compatibility with the copper interconnects of the lower wafer. Recessed channel transistors (that allow a transistor to be defined with sub-400C processes such as etch and deposition, are used for the upper layers. And finally, the layer to layer interconnect for the 3D stack is accomplished at close to full lithographic resolution and alignment.

    Or-Bach notes that MonolithIC 3D has approaches for the distinct differing needs of logic, DRAM, NAND, and other silicon device processing.

    This is intriguing technology, and it is an approach that could define the next direction of transistor production for a long time. With standard scaling costs becoming prohibitive, building up is the logical approach. MonolithIC 3D’s approach allows a designer to build levels upon levels of transistors, which is much more flexible, cost-effective, and open than the TSV approach of stacking and connecting finished die.

    MonolithIC 3D is at SEMICON West 2011, Booth 5585, and at


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