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    « A Technology Play for 3D Packaging; Decision Time for 3D Test | Main | Forging Ahead with 450mm Manufacturing »
    Wednesday
    Jul112012

    A Giant Leap? An Evolutionary Path? How All Roads Lead to 3D

    by Debra Vogler, Instant Insight Inc., Sunnyvale, CA

    With Intel already ramping its 22nm manufacturing process into high volume using its third-generation high-k metal gate and Tri-gate (fully-depleted) transistors, the company is advancing its Atom processor roadmap at twice the rate of Moore’s Law through 2014. In a pre-SEMICON West interview, Kaizad Mistry, Intel’s VP of logic technology integration, told SEMI that the company will be extending its Tri-gate to 14nm, with a second generation fin-based architecture.

    How will the rest of the industry fare with the introduction of 3D transistors? The point at which leading-edge IC manufacturers move to 3D will be different for each one, and will depend on each company’s specific product offerings and applications. “From a bulk perspective, the industry is starting to move into a tri-gate and FinFET-based structure,” said Raj Jammy, VP of materials and emerging technologies, SEMATECH. “The folks who continue to use SOI-based technology enjoy an advantage in that they can scale on SOI for a little while longer, but eventually, the expectation is that everyone will have to move to a 3D device.”

    Steve Longoria, SVP of business development at Soitec, makes the case for the evolutionary path to a 3D transistor architecture, which will probably have to be made by everyone at the 14nm node (Fig. 1). He views the SOI-based technology as a bridge for the industry. By starting with a fully-depleted planar transistor on an SOI wafer at 28nm (using Soitec’s FD-2D wafer, which STMicroelectronics has done), the industry can get the power and performance benefits of a fully-depleted transistor. Then, once the industry is ready to implement 3D ICs at 14nm, the company’s FD-3D wafer would come into play. “The FD-3D pre-defines the fin height, and the buried oxide layer provides built-in intrinsic isolation,” explained Longoria.

     

     Figure 1. The Soitec roadmap. SOURCE: Soitec 

    While the microprocessor manufacturers make their choices about which path to take to get to 3D ICs and when to make the jump, memory manufacturers also have some scaling choices to consider – but here, “3D” includes the packaging technology. “We see DRAM extendibility until probably 2020, and then after 2020, we think we’ll probably see the spin torque transfer MRAM come in,” noted Mark Thirsk, managing parter, Linx Consulting. “But the big transition between now and then is 3D (TSV-based) packaging technology,” which he views as taking up the slack in DRAM scaling.

    Thirsk maintains that NAND will be more difficult. “Does NAND go 3D and stay with a floating gate structure, or do we add in a charge trap approach – or do we go to something that looks like a resistive or ferroelectric approach?” mused Thirsk. He believes that this competitive NAND technology challenge has to be solved in the next two or three iterations of NAND. “So in the next two-to-four years, we need to be quite clear on what the next-generation is, and I don’t think that clarity exists today.”

    Adding to the uncertainty is that early work on charge trapping shows it doesn’t solve all the problems. And floating-gate technology in 3D, while probably a first approach, will be difficult because 3D is quite difficult to stack. “The ITRS, in the very far-out years, is calling for 128 layers for the most advanced devices,” observed Thirsk. “Most people we’ve talked to say that’s a pipe dream – it can’t happen.” He speculates that the limit on stacked layers is probably in the range of 32 to 64. “Again, 3D packaging (TSVs) will be needed to help in 3D NAND.”

     

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